FCP104N60 ? n-channel superfet ? ii mosfet ?2014 fairchild semiconductor corporation FCP104N60 rev. c0 www.fairchildsemi.com 1 june 2014 absolute maximum ratings t c = 25 o c unless otherwise noted. thermal characteristics symbol parameter FCP104N60 unit v dss drain to source voltage 600 v v gss gate to source voltage - dc 20 v - ac (f > 1 hz) 30 i d drain current - continuous (t c = 25 o c) 37 a - continuous (t c = 100 o c) 24 i dm drain current - pulsed (note 1) 111 a e as single pulsed avalanche energy (note 2) 809 mj i ar avalanche current (note 1) 6.8 a e ar repetitive avalanche energy (note 1) 3.57 mj dv/dt mosfet dv/dt 100 v/ns peak diode recovery dv/dt (note 3) 20 p d power dissipation (t c = 25 o c) 357 w - derate above 25 o c2.85w/ o c t j , t stg operating and storage temperature range -55 to +150 o c t l maximum lead temperature for soldering, 1/8? from case for 5 seconds 300 o c symbol parameter FCP104N60 unit r jc thermal resistance, junction to case, max. 0.35 o c/w r ja thermal resistance, junction to ambient, max. 40 FCP104N60 n-channel superfet ? ii mosfet 600 v, 37 a, 104 m features ? 650 v @ t j = 150c ?typ. r ds(on) = 96 m ? ultra low gate charge (typ. q g = 63 nc) ? low effective output capacitance (typ. c oss(eff.) = 280 pf) ? 100% avalanche tested ?rohs compliant applications ? telecom / sever power supplies ? industrial power supplies description superfet ? ii mosfet is fairchil d semiconductor?s brand-new high voltage super-junction (sj) mosf et family that is utilizing charge balance technology for outstanding low on-resistance and lower gate charge performance. this advanced technology is tailored to minimize c onduction loss, provide superior switching performance, and withstand extreme dv/dt rate and higher avalanche energy. cons equently, superfet ii mosfet is suitable for various ac/dc power conversion for system miniaturization and higher efficiency. to-220 g d s g s d
www.fairchildsemi.com 2 ?2014 fairchild semiconductor corporation FCP104N60 rev. c0 FCP104N60 ? n-ch annel superfet ? ii mosfet package marking and ordering information electrical characteristics t c = 25 o c unless otherwise noted. off characteristics on characteristics dynamic characteristics switching characteristics drain-source diod e characteristics part number top mark package packing method reel size tape width quantity FCP104N60 FCP104N60 to-220 tube n/a n/a 50 units symbol parameter test conditions min. typ. max. unit bv dss drain to source breakdown voltage v gs = 0 v, i d = 10 ma, t j = 25 c 600 - - v v gs = 0 v, i d = 10 ma, t j = 150 c 650 - - v bv dss / t j breakdown voltage temperature coefficient i d = 10 ma, referenced to 25 o c - 0.67 - v/ o c i dss zero gate voltage drain current v ds = 600 v, v gs = 0 v - - 1 a v ds = 480 v, v gs = 0 v,t c = 125 o c - 1.98 - i gss gate to body leakage current v gs = 20 v, v ds = 0 v - - 100 na v gs(th) gate threshold voltage v gs = v ds , i d = 250 a2.5-3.5v r ds(on) static drain to source on resistance v gs = 10 v, i d = 18.5 a - 96 104 m g fs forward transconductance v ds = 20 v, i d = 18.5 a -33-s c iss input capacitance v ds = 380 v, v gs = 0 v, f = 1 mhz - 3130 4165 pf c oss output capacitance - 75 100 pf c rss reverse transfer capacitance - 3.66 - pf c oss(eff.) effective output capacitance v ds = 0 v to 480 v, v gs = 0 v - 280 - pf q g(tot) total gate charge at 10v v ds = 380 v, i d = 18.5 a, v gs = 10 v (note 4) -6382nc q gs gate to source gate charge - 14 - nc q gd gate to drain ?miller? charge - 15 - nc esr equivalent series resistance f = 1 mhz - 0.97 - t d(on) turn-on delay time v dd = 380 v, i d = 18.5 a, v gs = 10 v, r g = 4.7 (note 4) -2662ns t r turn-on rise time - 18 46 ns t d(off) turn-off delay time - 72 154 ns t f turn-off fall time - 3.3 17 ns i s maximum continuous drain to source diode forward current - - 37 a i sm maximum pulsed drain to source diode forward current - - 114 a v sd drain to source diode forward voltage v gs = 0 v, i sd = 18.5 a - - 1.2 v t rr reverse recovery time v gs = 0 v, i sd = 18.5 a, di f /dt = 100 a/ s - 414 - ns q rr reverse recovery charge - 8.8 - c notes: 1. repetitive rating: pulse width limi ted by maximum junction temperature. 2. i as = 6.8 a, r g = 25 , starting t j = 25 c 3. i sd 18.5 a, di/dt 200 a/ s, v dd 380 v, starting t j = 25 c 4. essentially independent of operating temperature.
www.fairchildsemi.com 3 ?2014 fairchild semiconductor corporation FCP104N60 rev. c0 FCP104N60 ? n-ch annel superfet ? ii mosfet typical performance characteristics figure 1. on-region characteristics figure 2. transfer characteristics figure 3. on-resistance variation vs. figure 4. body diode forward voltage drain current and gate vo ltage variation vs. source current and temperature figure 5. capacitance characteristics figure 6. gate charge characteristics 0.3 1 10 20 1 10 100 *notes: 1. 250 s pulse test 2. t c = 25 o c i d , drain current[a] v ds , drain-source voltage[v] v gs = 10.0v 8.0v 6.0v 5.5v 5.0v 4.5v 4.0v 234567 1 10 100 200 -55 o c 150 o c *notes: 1. v ds = 10v 2. 250 s pulse test 25 o c i d , drain current[a] v gs , gate-source voltage[v] 0.00.30.60.91.21.5 0.001 0.01 0.1 1 10 100 200 *notes: 1. v gs = 0v 2. 250 s pulse test 150 o c i s , reverse drain current [a] v sd , body diode forward voltage [v] 25 o c 0 20406080100 0.08 0.12 0.16 0.20 0.24 *note: t c = 25 o c v gs = 20v v gs = 10v r ds(on) [ ], drain-source on-resistance i d , drain current [a] 0.1 1 10 100 600 0.1 1 10 100 1000 10000 20000 c oss c iss c iss = c gs + c gd (c ds = shorted) c oss = c ds + c gd c rss = c gd *note: 1. v gs = 0v 2. f = 1mhz c rss capacitances [pf] v ds , drain-source voltage [v] 0 1428425670 0 2 4 6 8 10 v ds = 120v v ds = 300v v ds = 480v *note: i d = 18.5a v gs , gate-source voltage [v] q g , total gate charge [nc]
www.fairchildsemi.com 4 ?2014 fairchild semiconductor corporation FCP104N60 rev. c0 FCP104N60 ? n-ch annel superfet ? ii mosfet typical performance characteristics (continued) figure 7. breakdown voltage variation figu re 8. on-resistance variation vs. temperature vs. temperature figure 9. maximum safe operating area figure 10. maximum drain current vs. case t emperature figure 11. eoss vs. drain to source voltage -100 -50 0 50 100 150 200 0.8 0.9 1.0 1.1 1.2 *notes: 1. v gs = 0v 2. i d = 10ma bv dss , [normalized] drain-source breakdown voltage t j , junction temperature [ o c] -100 -50 0 50 100 150 200 0.5 1.0 1.5 2.0 2.5 *notes: 1. v gs = 10v 2. i d = 18.5a r ds(on) , [normalized] drain-source on-resistance t j , junction temperature [ o c] 25 50 75 100 125 150 0 10 20 30 40 i d , drain current [a] t c , case temperature [ o c] 1 10 100 1000 0.01 0.1 1 10 100 300 10 s 100 s 1ms 10ms i d , drain current [a] v ds , drain-source voltage [v] operation in this area is limited by r ds(on) *notes: 1. t c = 25 o c 2. t j = 150 o c 3. single pulse dc 0 120 240 360 480 600 0 4 8 12 16 20 e oss , [ j] v ds , drain to source voltage [v]
www.fairchildsemi.com 5 ?2014 fairchild semiconductor corporation FCP104N60 rev. c0 FCP104N60 ? n-ch annel superfet ? ii mosfet typical characteristics (continued) figure 12 . transient thermal response curve 10 -5 10 -4 10 -3 10 -2 10 -1 110 1e-3 0.01 0.1 1 0.01 0.1 0.2 0.05 0.02 *notes: 1. z jc (t) = 0.35 o c/w max. 2. duty factor, d= t 1 /t 2 3. t jm - t c = p dm * z jc (t) 0.5 single pulse thermal response [z jc ] rectangular pulse duration [sec] t 1 p dm t 2
www.fairchildsemi.com 6 ?2014 fairchild semiconductor corporation FCP104N60 rev. c0 FCP104N60 ? n-ch annel superfet ? ii mosfet figure 13. gate charge test circuit & waveform figure 14. resistive switchin g test circuit & waveforms figure 15. unclamped inductive switching test circuit & waveforms v gs v ds 10% 90% t d(on) t r t on t off t d(off) t f v dd 10v v ds r l dut r g v gs v gs v ds 10% 90% t d(on) t r t on t off t d(off) t f v dd 10v v ds r l dut r g v gs v gs v gs i g = const.
www.fairchildsemi.com 7 ?2014 fairchild semiconductor corporation FCP104N60 rev. c0 FCP104N60 ? n-ch annel superfet ? ii mosfet figure 16. peak diode recovery dv/dt test circuit & waveforms dut v ds + _ driver r g same type as dut v gs ? dv/dt controlled by r g ?i sd controlled by pulse period v dd l i sd 10v v gs ( driver ) i sd ( dut ) v ds ( dut ) v dd body diode forward voltage drop v sd i fm , body diode forward current body diode reverse current i rm body diode recovery dv/dt di/dt d = gate pulse width gate pulse period -------------------------- dut v ds + _ driver r g same type as dut v gs ? dv/dt controlled by r g ?i sd controlled by pulse period v dd l l i sd 10v v gs ( driver ) i sd ( dut ) v ds ( dut ) v dd body diode forward voltage drop v sd i fm , body diode forward current body diode reverse current i rm body diode recovery dv/dt di/dt d = gate pulse width gate pulse period -------------------------- d = gate pulse width gate pulse period --------------------------
www.fairchildsemi.com 8 ?2014 fairchild semiconductor corporation FCP104N60 rev. c0 FCP104N60 ? n-ch annel superfet ? ii mosfet mechanical dimensions figure 17. to-220, molded, 3lead, jedec variation ab package drawings are provided as a service to customers considering fairchild com ponents. drawings may change in any manner without notice. please note the revision and/or date on the draw ing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild? s worldwide terms and conditions, specif- ically the warranty therein, which covers fairchild products. always visit fairchild semiconduc tor?s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/package/packagedetails.html?id=pn_tt220-003
www.fairchildsemi.com 9 ?2014 fairchild semiconductor corporation FCP104N60 rev. c0 FCP104N60 ? n-channel superfet ? ii mosfet trademarks the following includes registered and unregistered trademarks an d service marks, owned by fair child semiconductor and/or its gl obal subsidiaries, and is not intended to be an exhaustive lis t of all such trademarks. *trademarks of system gene ral corporation, used under license by fairchild semiconductor. disclaimer fairchild semiconductor reserves the right to make changes wi thout further notice to any products herein to improve reliability, function, or design. fairchild does not assume an y liability arising out of the application or use of any product or circuit described herein; neither does it convey an y license under its patent rights, nor the rights of others. these specifications do not expand the terms of fairchild?s wo rldwide terms and conditions, specifically the warranty therein, which covers these products. life support policy fairchild?s products are not authorized for use as critical components in life support de vices or systems without the express written approval of fairchild se miconductor corporation. as used here in: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a sign ificant injury of the user. 2. a critical component in any component of a life support, device, or system whose failure to perform can be reasonabl y expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. product status definitions definition of terms accupower? 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